1. Field of the Invention
This invention relates generally to nonvolatile EPROM and flash EEPROM circuits, and more particularly to techniques of isolating unselected cells during programming and reading of selected cells in EPROM and flash EEPROM arrays.
2. Discussion of the Prior Art
Referring to FIG. 1, a typical prior art erasable programmable read only memory (EPROM) 10 comprises an array of EPROM transistors or cells (of which for the sake of clarity only nine cells T1-T9 are shown) sharing drain regions D1-D9 which are connected to array bitlines BLa-BLc sharing common source regions connected to a hardwire line Vss1 to ground, and having control gates C1-C9 which are shared as array wordlines WLa-WLc. FIG. 2 shows a prior art N-channel enhancement mode EPROM cell 20 in a cross-section across control gate 22. The shared second layer polycrystalline silicon (poly2) control gate 22 is stacked on top of oxide or nitride/oxide dielectric film 24, which lies over poly1 floating gate 26, which lies over thermally grown thin oxide layer 28 over channel 30 between N++ source region 32S and N++ drain region 34D in P-type silicon substrate 36.
The FIG. 1 prior art EPROM array 10 is typically laid out in rows and columns on substrate 36 as partially shown in FIG. 3. In columns Ca and Cb transistors T1, T4 and T2, T5 have their drain regions D1, D4 and D2, D5 connected through contacts CD1, CD4 and CD2, CD5, respectively, by metal bitlines (omitted for the sake of clarity) overlying insulation on poly2 wordlines WLa and WLb. Common source region Sa-b is connected through contact CS by a Vss hardwire metal line, also not shown, running over insulation, to a ground terminal. Poly2 control gate wordlines WLa and WLb run over rows of poly1 floating gates F1, F2, and F4, F5 in columns Ca and Cb between the discrete drain regions and common source region Sa-b to form conventional fully self-aligned EPROM cells T1, T2, T4 and T5.
An EPROM cell 20 in the unprogrammed state (before programming or after erasure by ultra-violet light), has essentially no electron charge residing on floating gate 26, and the cell has a low switching voltage threshold Vt1 requiring only about 1.5 volts on control gate 22 to establish conduction through channel 30. To program the cell to a state with a high switching voltage threshold Vth, a high (up to 8V) drain programming voltage Vdp is pulsed to drain 34d and a higher (up to 14V) control gate programming voltage Vcp is pulsed to control gate 22, while both the source 32S voltage Vs and the substrate 36 voltage Vbb are held at zero. The high programming drain voltage Vdp and control gate voltage Vcp bias EPROM transistor 20 into its saturation condition and control gate 22 is capacitively coupled to active channel region 30 to establish a strong vertical electrical field which exerts a high (8 to 10) voltage on floating gate 26. The vertical field generates many hot electrons in channel 30 at the pinch-off region close to the drain junction, some of which are attracted toward floating gate 26 with sufficient kinetic energy to surmount the Si-Si02 interoxide barrier, penetrate floating gate oxide layer 28, become trapped inside floating gate 26 and raise the threshold voltage Vt to a programmed high (normally above 5 volts) level Vth.
Generally, EPROMS are programmed at a high drain voltage Vdp in order to generate maximum quantities of channel hot electrons. If a selected cell T5 (FIG. 1) is programmed by applying Vdp=8 volts to its drain D5 bitline BLb and applying Vcp=14 volts to its gate C5 wordline WLb, then, on the selected bitline BLb, the unselected cells T2 and T8 also receive 8 volts on their drains D2 and D8 while receiving zero volts on their control gates C2 and C8. FIG. 4 shows the equivalent circuit for the adjacent unselected cells Tun=T2 and T8 with drains on the selected bitline Blb. The high Vdp on bitline BLb shared by unselected cell drains D2 and D8 couples to their floating gates F2 and F8, slightly turning on unselected cells T2 and T8 to conduct leakage currents. This is a "grounded gate turn-on" or "grounded gate drain breakdown" (so-called BVDSS) condition. The lower the BVDSS. Breakdown Voltage Between the Drain and the Source when the gate is shorted to the source ("BVDSS"), the higher the leakage current. If a high density memory array 10 incorporates 1,000 wordlines and if at this high drain programming voltage Vdp on a selected bitline, each unselected cell has a 1uA leakage current, the selected bitline has a 1mA leakage current added to the programming current (about 0.5mA-1.0mA) for the selected cell. At worst, leakage currents can exceed 1mA. High/low density EPROM memory cell's BVDSS vary cell by cell, chip by chip, and wafer by wafer. Therefore, conventional high/low density and high/regular speed nonvolatile EPROM cells require a BVDSS guardband for a margin of safety. Prior art cells using a drain programming voltage of Vdp=8 volts needed a high drain breakdown voltage of around 10 to 11 volts to guarantee suitable unselected cell isolation and programmability. This drain breakdown voltage limitation makes it difficult to scale down the prior art EPROM cell channel length and implant concentration. Programming isolation is a major concern when a conventional EPROM cell channel length is scaled down to short channel regions (such as 1.0um). This high BVDSS criteria in a conventional EPROM cell 20 requires increasing the doping concentration in channel region 30, which undesirably significantly reduces cell 20 current, increases the bitline junction capacitance, and limits the scale-down capability of the channel 30 length and of the cell 20 size. Thus, high density megabit EPROMs have been hard to produce at high yield rates with consistently optimized array programmability and high read/write speeds. Alleviating the BVDSS guardband constraint could facilitate manufacturing EPROM arrays with more consistent programmability, smaller size, higher read access speed, and higher manufacturing yields.
Referring to FIG. 5, U.S. Pat. No. 4,328,565 to Harari teaches an EPROM cell 50 in which control gate 52,52' extends beyond the left edge 56L of floating gate 56,56' and beyond underlying (first) channel portion 61 towards source region 62S to overlap substrate 66 and form a control gate (second) channel portion 62 extending from first channel portion 61 in series to source region 62S. Control gate 52,52' is less strongly capacitively coupled to drain 64D and does not invert the second channel portion 62 in an unselected cell when drain region 64D of that cell is subjected to a high Vdp during programming of an adjacent selected cell. The non-inverted second channel portion 62 blocks leakage current from flowing through first channel portion 61. The two channel portions 61 and 62 are manufactured simultaneously, and hence their combined total length 60 is constantly defined by a mask (not shown). However, each portion's separate length is inconstantly defined by the non-self-aligned gates 52,52' and 56,56', and these inconstant channel portion lengths 61 and 62 result in inconstant programmability and read current in Harari's cell.
FIG. 5 also shows how, in a partially self-aligned split gate EPROM as disclosed by Eitan in U.S. Pat. No. 4,639,893, the floating gate channel length 61 (which is more important than the total channel length 60) can be consistently defined by the poly1 floating gate 56 length (omitting floating gate portion 56') and by the drain 64D N++ion implant which is self-aligned to the right edge 57 of poly1 floating gate 56. The control gate 52,52' (MOS) channel length 62 is not consistent but rather depends upon the alignment of the source 62S and drain 64D N++ion implant mask (not shown) which is not perfectly aligned to poly1 gate 56. Therefore, in Eitan the total channel length 60 is not constant, which compromises the cell 50 read current distribution. A too-short channel 60 can cause channel "punchthrough" conduction from drain 64D, when at high voltage, to source 62S. These non-alignment constraints do not allow making the control gate channel length 62 too short, and thereby limit scaling down the dimensions of such a prior art partially self-aligned split gate EPROM cell 50.
As shown in FIG. 6 Eitan exploits the constant floating gate channel length 61 to increase array density by using a virtual ground array structure in which, during programming cell T14, all unselected bitlines BLd, BLe and BLg and unselected wordlines WLd and WLf are clamped at the ground (zero volts) potential while high voltages are applied to selected wordline WLe and bitline BLf. Bitline BLf is shared (as the source) by adjacent unselected cell T15. In cell T15 hot electrons will be injected toward the control gate 52,52' and surface states may be generated at the source side 62S. A portion of these channel hot electrons reach and become trapped inside of the floating gate 56 of T15, to a degree dependent upon the electrical field between the T15 floating gate and the T15 channel surface beneath the left edge of its floating gate. Surface states and trapped electrons both increase the cell T15 threshold voltage Vt and compromise its reliability. Another problem of this prior art EPROM structure is that for each cell T10-T18 programming current is effectively doubled, which diminishes the attractiveness and practicality of multiplebyte programming.
FIG. 5 further shows how a prior art overlapping control gate cell can be modified as described by Samachisa et al. in an article entitled "A 128K Flash EEPROM Using Double-Polysilicon Technology" in the IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 5, Oct. 1987. The flash EEPROM array cells are all erased simultaneously by application of a high (19V) voltage on the drain with the source and gate grounded. Unlike UV erasure, this usually over-erases the floating gate, leaving the floating gate with a positive charge so that the flash EEPROM is a (normally-on) depletion mode transistor ready to conduct leakage current when an adjacent cell is selected for programming or reading. The cell's total channel length 60 is constantly defined by the poly2 mask (not shown) between control gate 52 left edge 51 and right edge 53. However, only the right edge 57 of poly1 floating gate 56 is self-aligned to edge 53 of poly2 control gate 52, so neither the floating gate channel length 61 nor the control gate channel length 62 is constant. This flash EEPROM cell has more drawbacks than the Eitan partially self-aligned cell because the flash EEPROM variable floating gate channel length 61 and resulting uncontrollable MOS punch-through voltage and read current cause programming inconsistency and limit scale-down of the cell.
Thus, there remains a need for shorter and more constant length channels in EPROM cells isolated from drain turn-on conditions in order to achieve high efficiency and consistent programming, fast read speed, and scale-down ability without sacrificing performance for high or low density EPROM or flash EEPROM products.